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GSR001

The GSR001 series is a system-on-chip product optimized for low power, audio record and playback with an embedded ARM® Cortex™-M0 32-bit microcontroller core.
The GSR001 device embeds a Cortex™-M0 core running up to 50 MHz with 64K/128Kbyte of non-volatile flash memory and 12K-byte of embedded SRAM. It also comes equipped with a variety of peripheral devices, such as Timers, Watchdog Timer (WDT), Real-time Clock (RTC), Peripheral Direct Memory Access (PDMA), a variety of serial interfaces (UART, SPI/SSP, I 2 C, I 2 S), PWM modulators,
GPIO, LDO, SDADC, SARADC, DPWM, Low Voltage Detector and Brown-out detector.
The GSR001 comes equipped with a rich set of power saving modes including a Deep Power Down (DPD) mode drawing less than 1uA. A micro-power 10KHz oscillator can periodically wake up the device from deep power down to check for other events. A Standby Power Down (SPD) mode can maintain a real time clock function at less than 5uA.
For audio functionality the GSR001 includes a Sigma-Delta ADC with 91dB SNR performance coupled with a Programmable Gain Amplifier (PGA with 0-6/12dB gain) and volume control (36dB to - 108dB) in digital domain to enable direct connection of a microphone. Audio output is provided by a Differential Class D amplifier (DPWM) that can deliver 0.5W of power to an 8Ω speaker.
The GSR001 provides 16 analog enabled general purpose IO pins (GPIO). These pins can be configured to connect to an analog comparator, can be configured as analog current sources or can be routed to the SDADC for analog conversion. They can also be used as a relaxation oscillator to perform capacitive touch sensing.

特性

  • Core
    – ARM® Cortex™-M0 core running up to 50 MHz for normal speed.
    – One 24-bit System tick timer for operating system support.
    – Supports a variety of low power sleep and power down modes.
    – Single-cycle 32-bit hardware multiplier.
    – NVIC (Nested Vector Interrupt Controller) for 32 interrupt inputs, each with 4-levels of priority.
    – Serial Wire Debug (SWD) supports with 2 watchpoints/4 breakpoints.

  • Audio Analog to Digital converter
    – Sigma Delta ADC with configurable decimation filter and 16 bit output.
    – 90dB Signal-to-Noise (SNR) performance.
    – Programmable gain amplifier with 32 steps from -12 to 35.25dB in 0.75dB steps.
    – Boost gain stage of 26dB, giving maximum total gain of 61dB.
    – Input selectable from dedicated MIC pins or analog enabled GPIO.
    – Programmable biquad filter to support multiple sample rates from 8-32kHz.
    – DMA support for minimal CPU intervention.

  • SARADC
    – 12-bit SAR ADC with 350K SPS
    – Up to 12-ch single-end input
    – Single scan/single cycle scan/continuous scan
    – Each channel with individual result register
    – Scan on enabled channels
    – Threshold voltage detection
    – Conversion start by software programming or external input
    – Supports PDMA mode

  • I2S
    – Interface with external audio CODEC.
    – Operate as either master or slave.
    – Capable of handling 8, 16, 24 and 32 bit word sizes
    – Mono and stereo audio data supported
    – I 2 S and MSB justified data format supported
    – Two 8 word FIFO data buffers are provided, one for transmit and one for receive
    – Generates interrupt requests when buffer levels cross a programmable boundary
    – Supports DMA requests, for transmit and receive

  • Standby current in STOP mode with SRAM retention <=10µA at 25°C.

  • Operating Temperature: -40C~85C

  • Package:
    – All Green package (RoHS)

  • LQFP 64-pin

引脚图

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订购信息

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